patch-2.4.0-test8 linux/include/asm-i386/system.h

• Lines: 16
• Date: Fri Sep 8 12:52:41 2000
• Orig file: v2.4.0-test7/linux/include/asm-i386/system.h
• Orig date: Wed Aug 9 19:19:51 2000

diff -u --recursive --new-file v2.4.0-test7/linux/include/asm-i386/system.h linux/include/asm-i386/system.h
@@ -267,8 +267,15 @@
  * I expect future Intel CPU's to have a weaker ordering,
  * but I'd also expect them to finally get their act together
  * and add some real memory barriers if so.
+ *
+ * The Pentium III does add a real memory barrier with the
+ * sfence instruction, so we use that where appropriate.
  */
+#ifndef CONFIG_X86_XMM
 #define mb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
+#else
+#define mb()	__asm__ __volatile__ ("sfence": : :"memory")
+#endif
 #define rmb()	mb()
 #define wmb()	__asm__ __volatile__ ("": : :"memory")
 #define set_mb(var, value) do { xchg(&var, value); } while (0)