patch-2.4.0-test8 linux/include/asm-alpha/core_irongate.h

• Lines: 287
• Date: Mon Aug 28 21:21:57 2000
• Orig file: v2.4.0-test7/linux/include/asm-alpha/core_irongate.h
• Orig date: Sun Mar 19 18:35:31 2000

diff -u --recursive --new-file v2.4.0-test7/linux/include/asm-alpha/core_irongate.h linux/include/asm-alpha/core_irongate.h
@@ -83,247 +83,24 @@
 	igcsr32 agpmode;		/* 0xB0 - AGP/GART mode control */
 } Irongate0;
 
-/* Bitfield and mask register definitions */
 
-/* Device, vendor IDs - offset 0x00 */
+typedef struct {
 
-typedef union {
-	igcsr32 i;			/* integer value of CSR */
-	struct {
-		unsigned v : 16;
-		unsigned d : 16;
-	} r;				/* structured interpretation */
-} ig_dev_vendor_t;
-
-
-/* Status, command registers - offset 0x04 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned command;
-		unsigned status;
-	} s;
-	struct {
-		/* command register fields */
-		unsigned iospc : 1;		/* always reads zero */
-		unsigned memspc	 : 1;		/* PCI memory space accesses? */
-		unsigned iten : 1;		/* always 1: can be bus initiator */
-		unsigned scmon : 1;		/* always 0 special cycles not chckd */
-		unsigned mwic : 1;		/* always 0 - no mem write & invalid */
-		unsigned vgaps : 1;		/* always 0 - palette rds not special */
-		unsigned per : 1;		/* parity error resp: always 0 */
-		unsigned step : 1;		/* address/data stepping : always 0 */
-		unsigned serre : 1;		/* 1 = sys err output driver enable */
-		unsigned fbbce : 1;		/* fast back-back cycle : always 0 */
-		unsigned zero1 : 6;		/* must be zero */
-
-		/* status register fields */
-		unsigned zero2 : 4;	     /* must be zero */
-		unsigned cl : 1;	    /* config space capa list: always 1 */
-		unsigned pci66 : 1;	    /* 66 MHz PCI support - always 0 */
-		unsigned udf : 1;	    /* user defined features - always 0 */
-		unsigned fbbc : 1;	    /* back-back transactions - always 0 */
-		unsigned ppe : 1;	    /* PCI parity error detected (0) */
-		unsigned devsel : 2;	    /* DEVSEL timing (always 01) */
-		unsigned sta : 1;	    /* signalled target abort (0) */
-		unsigned rta : 1;	    /* recvd target abort */
-		unsigned ria : 1;	    /* recvd initiator abort */
-		unsigned serr : 1;	    /* SERR has been asserted */
-		unsigned dpe : 1;	    /* DRAM parity error (0) */
-	} r;
-} ig_stat_cmd_t;
-
-
-/* Revision ID, Programming interface, subclass, baseclass - offset 0x08 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		/* revision ID */
-		unsigned step : 4;		/* stepping Revision ID */
-		unsigned die : 4;		/* die Revision ID */
-		unsigned pif : 8;		/* programming interface (0x00) */
-		unsigned sub : 8;		/* subclass code (0x00) */
-		unsigned base: 8;		/* baseclass code (0x06) */
-	} r;
-} ig_class_t;
-
-
-/* Latency Timer, PCI Header type - offset 0x0C */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned zero1:8;		/* reserved */
-		unsigned lat : 8;		/* latency in PCI bus clocks */
-		unsigned hdr : 8;		/* PCI header type */
-		unsigned zero2:8;		/* reserved */
-	} r;
-} ig_latency_t;
-
-
-/* Base Address Register 0 - offset 0x10 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned mem : 1;		/* Reg pts to memory (always 0) */
-		unsigned type: 2;		/* 32 bit register = 0b00 */
-		unsigned pref: 1;		/* graphics mem prefetchable=1 */
-		unsigned baddrl : 21;		/* 32M = minimum alloc -> all zero */
-		unsigned size : 6;		/* size requirements for AGP */
-		unsigned zero : 1;		/* reserved=0 */
-	} r;
-} ig_bar0_t;
-
-
-/* Base Address Register 1 - offset 0x14 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned mem : 1;		/* BAR0 maps to memory -> 0 */
-		unsigned type : 2;		/* BAR1 is 32-bit -> 0b00 */
-		unsigned pref : 1;		/* graphics mem prefetchable=1 */
-		unsigned baddrl : 8;		/* 4K alloc for AGP CSRs -> 0b00 */
-		unsigned baddrh : 20;		/* base addr of AGP CSRs A[30:11] */
-	} r;
-} ig_bar1_t;
-
-
-/* Base Address Register 2 - offset 0x18 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned io  : 1;		/* BAR2 maps to I/O space -> 1 */
-		unsigned zero1: 1;		/* reserved */
-		unsigned addr : 22;		/* BAR2[31:10] - PM2_BLK base */
-		unsigned zero2: 8;		/* reserved */
-	} r;
-} ig_bar2_t;
-
-
-/* Capabilities Pointer - offset 0x34 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned cap : 8;		/* =0xA0, offset of AGP ctrl regs */
-		unsigned zero: 24;		/* reserved */
-	} r;
-} ig_capptr_t;
-
-
-/* Base Address Chip Select Register 1,0 - offset 0x40 */
-/* Base Address Chip Select Register 3,2 - offset 0x44 */
-/* Base Address Chip Select Register 5,4 - offset 0x48 */
-
-typedef union {
-
-	igcsr32 i;
-	struct {
-		/* lower bank */
-		unsigned en0 : 1;		/* memory bank enabled */
-		unsigned mask0 : 6;		/* Address mask for A[28:23] */
-		unsigned base0 : 9;		/* Bank Base Address A[31:23] */
-
-		/* upper bank */
-		unsigned en1 : 1;		/* memory bank enabled */
-		unsigned mask1 : 6;		/* Address mask for A[28:23] */
-		unsigned base1 : 9;		/* Bank Base Address A[31:23] */
-	} r;
-} ig_bacsr_t, ig_bacsr10_t, ig_bacsr32_t, ig_bacsr54_t;
-
-
-/* SDRAM Address Mapping Control Register - offset 0x50 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned z1 : 1;		/* reserved */
-		unsigned bnks0: 1;		/* 0->2 banks in chip select 0 */
-		unsigned am0 : 1;		/* row/column addressing */
-		unsigned z2 : 1;		/* reserved */
-
-		unsigned z3 : 1;		/* reserved */
-		unsigned bnks1: 1;		/* 0->2 banks in chip select 1 */
-		unsigned am1 : 1;		/* row/column addressing */
-		unsigned z4 : 1;		/* reserved */
-
-		unsigned z5 : 1;		/* reserved */
-		unsigned bnks2: 1;		/* 0->2 banks in chip select 2 */
-		unsigned am2 : 1;		/* row/column addressing */
-		unsigned z6 : 1;		/* reserved */
-
-		unsigned z7 : 1;		/* reserved */
-		unsigned bnks3: 1;		/* 0->2 banks in chip select 3 */
-		unsigned am3 : 1;		/* row/column addressing */
-		unsigned z8 : 1;		/* reserved */
-
-		unsigned z9 : 1;		/* reserved */
-		unsigned bnks4: 1;		/* 0->2 banks in chip select 4 */
-		unsigned am4 : 1;		/* row/column addressing */
-		unsigned z10 : 1;		/* reserved */
-
-		unsigned z11 : 1;		/* reserved */
-		unsigned bnks5: 1;		/* 0->2 banks in chip select 5 */
-		unsigned am5 : 1;		/* row/column addressing */
-		unsigned z12 : 1;		/* reserved */
-
-		unsigned rsrvd: 8;		/* reserved */
-	} r;
-} ig_drammap_t;
-
-
-/* DRAM timing and driver strength register - offset 0x54 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		/* DRAM timing parameters */
-		unsigned trcd : 2;
-		unsigned tcl : 2;
-		unsigned tras: 3;
-		unsigned trp : 2;
-		unsigned trc : 3;
-		unsigned icl: 2;
-		unsigned ph : 2;
-
-		/* Chipselect driver strength */
-		unsigned adra : 1;
-		unsigned adrb : 1;
-		unsigned ctrl : 3;
-		unsigned dqm : 1;
-		unsigned cs : 1;
-		unsigned clk: 1;
-		unsigned rsrvd:8;
-	} r;
-} ig_dramtm_t;
-
-
-/* DRAM Mode / Status and ECC Register - offset 0x58 */
-
-typedef union {
-	igcsr32 i;
-	struct {
-		unsigned chipsel : 6;		/* failing ECC chip select */
-		unsigned zero1 : 2;		/* always reads zero */
-		unsigned status : 2;		/* ECC Detect logic status */
-		unsigned zero2 : 6;		/* always reads zero */
-
-		unsigned cycles : 2;		/* cycles per refresh, see table */
-		unsigned en : 1;		/* ECC enable */
-		unsigned r : 1;			/* Large burst enable (=0) */
-		unsigned bre : 1;		/* Burst refresh enable */
-		unsigned zero3 : 2;		/* reserved = 0 */
-		unsigned mwe : 1;		/* Enable writes to DRAM mode reg */
-		unsigned type : 1;		/* SDRAM = 0, default */
-		unsigned sdraminit : 1;		/* SDRAM init - set params first! */
-		unsigned zero4 : 6;		/* reserved = 0 */
-	} r;
-} ig_dramms_t;
+	igcsr32 dev_vendor;		/* 0x00 - Device and Vendor IDs */
+	igcsr32 stat_cmd;		/* 0x04 - Status and Command regs */
+	igcsr32 class;			/* 0x08 - subclass, baseclass etc */
+	igcsr32 htype;			/* 0x0C - header type (at 0x0E) */
+	igcsr32 rsrvd0[2];		/* 0x10-0x17 reserved */
+	igcsr32 busnos;			/* 0x18 - Primary, secondary bus nos */
+	igcsr32 io_baselim_regs;	/* 0x1C - IO base, IO lim, AGP status */
+	igcsr32	mem_baselim;		/* 0x20 - memory base, memory lim */
+	igcsr32 pfmem_baselim;		/* 0x24 - prefetchable base, lim */
+	igcsr32 rsrvd1[2];		/* 0x28-0x2F reserved */
+	igcsr32 io_baselim;		/* 0x30 - IO base, IO limit */
+	igcsr32 rsrvd2[2];		/* 0x34-0x3B - reserved */
+	igcsr32 interrupt;		/* 0x3C - interrupt, PCI bridge ctrl */
+
+} Irongate1;
 
 
 /*
@@ -343,7 +120,21 @@
 #define IRONGATE_IO		(IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
 #define IRONGATE_CONF		(IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
 
-#define IRONGATE0		((Irongate0 *) IRONGATE_CONF)
+/*
+ * PCI Configuration space accesses are formed like so:
+ *
+ * 0x1FE << 24 |  : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
+ *                : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
+ *                  ---bus numer---   -device-- -fun-   ---register----
+ */
+
+#define IGCSR(dev,fun,reg)	( IRONGATE_CONF | \
+				((dev)<<11) | \
+				((fun)<<8) | \
+				(reg) )
+
+#define IRONGATE0		((Irongate0 *) IGCSR(0, 0, 0))
+#define IRONGATE1		((Irongate1 *) IGCSR(1, 0, 0))
 
 /*
  * Data structure for handling IRONGATE machine checks: