patch-2.4.0-test3 linux/include/asm-mips64/mmu_context.h

• Lines: 42
• Date: Sun Jul 9 22:18:15 2000
• Orig file: v2.4.0-test2/linux/include/asm-mips64/mmu_context.h
• Orig date: Tue May 23 15:31:36 2000

diff -u --recursive --new-file v2.4.0-test2/linux/include/asm-mips64/mmu_context.h linux/include/asm-mips64/mmu_context.h
@@ -17,6 +17,21 @@
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 
+/*
+ * For the fast tlb miss handlers, we currently keep a per cpu array
+ * of pointers to the current pgd for each processor. Also, the proc.
+ * id is stuffed into the context register. This should be changed to 
+ * use the processor id via current->processor, where current is stored
+ * in watchhi/lo. The context register should be used to contiguously
+ * map the page tables.
+ */
+#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
+	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
+#define TLBMISS_HANDLER_SETUP() \
+	set_context((unsigned long) smp_processor_id() << (23 + 3)); \
+	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+extern unsigned long pgd_current[];
+
 #ifndef CONFIG_SMP
 #define CPU_CONTEXT(cpu, mm)	(mm)->context
 #else
@@ -85,7 +100,8 @@
 	if ((CPU_CONTEXT(cpu, next) ^ ASID_CACHE(cpu)) & ASID_VERSION_MASK)
 		get_new_cpu_mmu_context(next, cpu);
 
-	set_entryhi(CPU_CONTEXT(cpu, next));
+	set_entryhi(CPU_CONTEXT(cpu, next) & 0xff);
+	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 }
 
 /*
@@ -110,7 +126,8 @@
 	/* Unconditionally get a new ASID.  */
 	get_new_cpu_mmu_context(next, smp_processor_id());
 
-	set_entryhi(CPU_CONTEXT(smp_processor_id(), next));
+	set_entryhi(CPU_CONTEXT(smp_processor_id(), next) & 0xff);
+	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 }
 
 #endif /* _ASM_MMU_CONTEXT_H */