patch-2.4.0-test3 linux/arch/mips/sni/pci.c

• Lines: 110
• Date: Sun Jul 9 22:18:15 2000
• Orig file: v2.4.0-test2/linux/arch/mips/sni/pci.c
• Orig date: Tue May 23 15:31:33 2000

diff -u --recursive --new-file v2.4.0-test2/linux/arch/mips/sni/pci.c linux/arch/mips/sni/pci.c
@@ -1,15 +1,15 @@
-/* $Id: pci.c,v 1.9 1999/12/04 03:59:00 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * SNI specific PCI support for RM200/RM300.
  *
- * Copyright (C) 1997, 1998, 1999 Ralf Baechle
+ * Copyright (C) 1997 - 2000 Ralf Baechle
  */
 #include <linux/config.h>
 #include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
@@ -23,10 +23,11 @@
 		return -1;                                                   \
 	*(volatile u32 *)PCIMT_CONFIG_ADDRESS =                              \
 		 ((dev->bus->number    & 0xff) << 0x10) |                    \
-	         ((dev->dev_fn & 0xff) << 0x08) |                            \
+	         ((dev->devfn & 0xff) << 0x08) |                             \
 	         (where  & 0xfc);                                            \
 } while(0);
 
+#if 0
 /* To do:  Bring this uptodate ...  */
 static void pcimt_pcibios_fixup (void)
 {
@@ -62,6 +63,7 @@
 		}
 	}
 }
+#endif
 
 /*
  * We can't address 8 and 16 bit words directly.  Instead we have to
@@ -148,6 +150,69 @@
 	pcimt_write_config_byte,
 	pcimt_write_config_word,
 	pcimt_write_config_dword
+};
+
+void __init
+pcibios_fixup_bus(struct pci_bus *b)
+{
+}
+
+void
+pcibios_update_resource(struct pci_dev *dev, struct resource *root,
+			struct resource *res, int resource)
+{
+	u32 new, check;
+	int reg;
+
+	new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
+	if (resource < 6) {
+		reg = PCI_BASE_ADDRESS_0 + 4*resource;
+	} else if (resource == PCI_ROM_RESOURCE) {
+		res->flags |= PCI_ROM_ADDRESS_ENABLE;
+		new |= PCI_ROM_ADDRESS_ENABLE;
+		reg = dev->rom_base_reg;
+	} else {
+		/* Somebody might have asked allocation of a non-standard resource */
+		return;
+	}
+	
+	pci_write_config_dword(dev, reg, new);
+	pci_read_config_dword(dev, reg, &check);
+	if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
+		printk(KERN_ERR "PCI: Error while updating region "
+		       "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
+		       new, check);
+	}
+}
+
+void __init pcibios_init(void)
+{
+	struct pci_ops *ops = &sni_pci_ops;
+
+	pci_scan_bus(0, ops, NULL);
+}
+
+int __init pcibios_enable_device(struct pci_dev *dev)
+{
+	/* Not needed, since we enable all devices at startup.  */
+	return 0;
+}
+
+void __init
+pcibios_align_resource(void *data, struct resource *res, unsigned long size)
+{
+}
+
+char * __init
+pcibios_setup(char *str)
+{
+	/* Nothing to do for now.  */
+
+	return str;
+}
+
+struct pci_fixup pcibios_fixups[] = {
+	{ 0 }
 };
 
 #endif /* CONFIG_PCI */