patch-2.4.0-test2 linux/include/asm-arm/proc-armv/assembler.h

• Lines: 103
• Date: Mon Jun 19 17:59:35 2000
• Orig file: v2.4.0-test1/linux/include/asm-arm/proc-armv/assembler.h
• Orig date: Fri Oct 22 13:21:53 1999

diff -u --recursive --new-file v2.4.0-test1/linux/include/asm-arm/proc-armv/assembler.h linux/include/asm-arm/proc-armv/assembler.h
@@ -1,10 +1,10 @@
 /*
  * linux/asm-arm/proc-armv/assembler.h
  *
- * Copyright (C) 1996 Russell King
+ * Copyright (C) 1996-2000 Russell King
  *
- * This file contains arm architecture specific defines
- * for the different processors
+ * This file contains ARM processor specifics for
+ * the ARM6 and better processors.
  */
 #ifndef __ASSEMBLY__
 #error "Only include this from assembly code"
@@ -19,68 +19,36 @@
 
 /*
  * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
- * RETINSTR - return instruction (eg, mov pc, lr)
  */
 #ifdef __STDC__
 #define LOADREGS(cond, base, reglist...)\
 	ldm##cond	base,reglist
-
-#define RETINSTR(instr, regs...)\
-	instr	regs
 #else
 #define LOADREGS(cond, base, reglist...)\
 	ldm/**/cond	base,reglist
-
-#define RETINSTR(instr, regs...)\
-	instr		regs
 #endif
 
 /*
- * No nop required after mode change
- */
-#define MODENOP
-
-/*
- * Change to `mode'
- */
-#define MODE(savereg,tmpreg,mode) \
-	mrs	savereg, cpsr; \
-	bic	tmpreg, savereg, $0x1f; \
-	orr	tmpreg, tmpreg, $mode; \
-	msr	cpsr, tmpreg
-
-/*
- * Restore mode
+ * Build a return instruction for this processor type.
  */
-#define RESTOREMODE(savereg) \
-	msr	cpsr, savereg
-
-/*
- * save interrupt state (uses stack)
- */	
-#define SAVEIRQS(tmpreg)\
-	mrs	tmpreg, cpsr; \
-	str	tmpreg, [sp, $-4]!
-
-/*
- * restore interrupt state (uses stack)
- */
-#define RESTOREIRQS(tmpreg)\
-	ldr	tmpreg, [sp], $4; \
-	msr	cpsr, tmpreg
-
-/*
- * disable IRQs
- */
-#define DISABLEIRQS(tmpreg)\
-	mrs	tmpreg , cpsr; \
-	orr	tmpreg , tmpreg , $I_BIT; \
-	msr	cpsr, tmpreg
+#define RETINSTR(instr, regs...)\
+	instr	regs
 
 /*
- * enable IRQs
- */
-#define ENABLEIRQS(tmpreg)\
-	mrs	tmpreg , cpsr; \
-	bic	tmpreg , tmpreg , $I_BIT; \
-	msr	cpsr, tmpreg
+ * Save the current IRQ state and disable IRQs
+ * Note that this macro assumes FIQs are enabled, and
+ * that the processor is in SVC mode.
+ */
+	.macro	save_and_disable_irqs, oldcpsr, temp
+	mrs	\oldcpsr, cpsr
+	mov	\temp, #I_BIT | MODE_SVC
+	msr	cpsr_c, \temp
+	.endm
+
+/*
+ * Restore interrupt state previously stored in
+ * a register
+ */
+	.macro	restore_irqs, oldcpsr
+	msr	cpsr_c, \oldcpsr
+	.endm