patch-2.4.0-test12 linux/include/asm-mips64/bitops.h

• Lines: 219
• Date: Tue Nov 28 21:42:04 2000
• Orig file: v2.4.0-test11/linux/include/asm-mips64/bitops.h
• Orig date: Wed Jul 5 22:15:26 2000

diff -u --recursive --new-file v2.4.0-test11/linux/include/asm-mips64/bitops.h linux/include/asm-mips64/bitops.h
@@ -1,11 +1,10 @@
-/* $Id: bitops.h,v 1.3 1999/08/20 21:59:08 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1994 - 1999  Ralf Baechle (ralf@gnu.org)
- * Copyright (c) 1999  Silicon Graphics, Inc.
+ * Copyright (c) 1994, 95, 96, 97, 98, 99, 2000  Ralf Baechle
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
  */
 #ifndef _ASM_BITOPS_H
 #define _ASM_BITOPS_H
@@ -22,12 +21,18 @@
 #include <asm/mipsregs.h>
 
 /*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+/*
  * These functions for MIPS ISA > 1 are interrupt and SMP proof and
  * interrupt friendly
  */
 
 extern __inline__ void
-set_bit(unsigned long nr, void *addr)
+set_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp;
@@ -37,12 +42,21 @@
 		"or\t%0, %2\n\t"
 		"scd\t%0, %1\n\t"
 		"beqz\t%0, 1b"
-		:"=&r" (temp), "=m" (*m)
-		:"ir" (1UL << (nr & 0x3f)), "m" (*m));
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & 0x3f)), "m" (*m)
+		: "memory");
+}
+
+/* WARNING: non atomic and it can be reordered! */
+extern __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 6);
+
+	*m |= 1UL << (nr & 0x3f);
 }
 
 extern __inline__ void
-clear_bit(unsigned long nr, void *addr)
+clear_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp;
@@ -52,12 +66,13 @@
 		"and\t%0, %2\n\t"
 		"scd\t%0, %1\n\t"
 		"beqz\t%0, 1b\n\t"
-		:"=&r" (temp), "=m" (*m)
-		:"ir" (~(1UL << (nr & 0x3f))), "m" (*m));
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (~(1UL << (nr & 0x3f))), "m" (*m));
 }
 
+
 extern __inline__ void
-change_bit(unsigned long nr, void *addr)
+change_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp;
@@ -72,7 +87,7 @@
 }
 
 extern __inline__ unsigned long
-test_and_set_bit(unsigned long nr, void *addr)
+test_and_set_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp, res;
@@ -85,14 +100,28 @@
 		"beqz\t%2, 1b\n\t"
 		" and\t%2, %0, %3\n\t"
 		".set\treorder"
-		:"=&r" (temp), "=m" (*m), "=&r" (res)
-		:"r" (1UL << (nr & 0x3f)), "m" (*m));
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x3f)), "m" (*m)
+		: "memory");
 
 	return res != 0;
 }
 
+extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int mask, retval;
+	volatile long *a = addr;
+
+	a += nr >> 6;
+	mask = 1 << (nr & 0x3f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+
+	return retval;
+}
+
 extern __inline__ unsigned long
-test_and_clear_bit(unsigned long nr, void *addr)
+test_and_clear_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp, res;
@@ -106,14 +135,28 @@
 		"beqz\t%2, 1b\n\t"
 		" and\t%2, %0, %3\n\t"
 		".set\treorder"
-		:"=&r" (temp), "=m" (*m), "=&r" (res)
-		:"r" (1UL << (nr & 0x3f)), "m" (*m));
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x3f)), "m" (*m)
+		: "memory");
 
 	return res != 0;
 }
 
+extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int     mask, retval;
+	volatile long    *a = addr;
+
+	a += nr >> 6;
+	mask = 1 << (nr & 0x3f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+
+	return retval;
+}
+
 extern __inline__ unsigned long
-test_and_change_bit(unsigned long nr, void *addr)
+test_and_change_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> 6);
 	unsigned long temp, res;
@@ -126,8 +169,9 @@
 		"beqz\t%2, 1b\n\t"
 		" and\t%2, %0, %3\n\t"
 		".set\treorder"
-		:"=&r" (temp), "=m" (*m), "=&r" (res)
-		:"r" (1UL << (nr & 0x3f)), "m" (*m));
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x3f)), "m" (*m)
+		: "memory");
 
 	return res != 0;
 }
@@ -167,9 +211,6 @@
 		"nop\n\t"
 		"subu\t%0,32\n\t"
 #endif
-#ifdef __MIPSEB__
-#error "Fix this for big endian"
-#endif /* __MIPSEB__ */
 		"li\t%1,1\n"
 		"1:\tand\t%2,$1,%1\n\t"
 		"beqz\t%2,2f\n\t"
@@ -179,13 +220,9 @@
 		".set\tat\n\t"
 		".set\treorder\n"
 		"2:"
-		: "=r" (res),
-		  "=r" (dummy),
-		  "=r" (addr)
-		: "0" ((signed int) 0),
-		  "1" ((unsigned int) 0xffffffff),
-		  "2" (addr),
-		  "r" (size)
+		: "=r" (res), "=r" (dummy), "=r" (addr)
+		: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
+		  "2" (addr), "r" (size)
 		: "$1");
 
 	return res;
@@ -197,14 +234,11 @@
 	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
 	int set = 0, bit = offset & 31, res;
 	unsigned long dummy;
-	
+
 	if (bit) {
 		/*
 		 * Look for zero in first byte
 		 */
-#ifdef __MIPSEB__
-#error "Fix this for big endian byte order"
-#endif
 		__asm__(".set\tnoreorder\n\t"
 			".set\tnoat\n"
 			"1:\tand\t$1,%4,%1\n\t"
@@ -215,11 +249,8 @@
 			".set\tat\n\t"
 			".set\treorder\n"
 			"1:"
-			: "=r" (set),
-			  "=r" (dummy)
-			: "0" (0),
-			  "1" (1 << bit),
-			  "r" (*p)
+			: "=r" (set), "=r" (dummy)
+			: "0" (0), "1" (1 << bit), "r" (*p)
 			: "$1");
 		if (set < (32 - bit))
 			return set + offset;