patch-2.4.21 linux-2.4.21/include/asm-ia64/sn/pci/bridge.h
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- Lines: 1203
- Date:
2003-06-13 07:51:38.000000000 -0700
- Orig file:
linux-2.4.20/include/asm-ia64/sn/pci/bridge.h
- Orig date:
2002-08-02 17:39:45.000000000 -0700
diff -urN linux-2.4.20/include/asm-ia64/sn/pci/bridge.h linux-2.4.21/include/asm-ia64/sn/pci/bridge.h
@@ -4,7 +4,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (c) 1992-1997,2000-2002 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_SN_PCI_BRIDGE_H
#define _ASM_SN_PCI_BRIDGE_H
@@ -12,9 +12,40 @@
/*
* bridge.h - header file for bridge chip and bridge portion of xbridge chip
+ *
+ * Also including offsets for unique PIC registers.
+ * The PIC asic is a follow-on to Xbridge and most of it's registers are
+ * identical to those of Xbridge. PIC is different than Xbridge in that
+ * it will accept 64 bit register access and that, in some cases, data
+ * is kept in bits 63:32. PIC registers that are identical to Xbridge
+ * may be accessed identically to the Xbridge registers, allowing for lots
+ * of code reuse. Here are the access rules as described in the PIC
+ * manual:
+ *
+ * o Read a word on a DW boundary returns D31:00 of reg.
+ * o Read a DW on a DW boundary returns D63:00 of reg.
+ * o Write a word on a DW boundary loads D31:00 of reg.
+ * o Write a DW on a DW boundary loads D63:00 of reg.
+ * o No support for word boundary access that is not double word
+ * aligned.
+ *
+ * So we can reuse a lot of bridge_s for PIC. In bridge_s are included
+ * #define tags and unions for 64 bit access to PIC registers.
+ * For a detailed PIC register layout see pic.h.
*/
+#include <linux/config.h>
#include <asm/sn/xtalk/xwidget.h>
+#ifndef CONFIG_IA64_SGI_SN1
+#include <asm/sn/pci/pic.h>
+
+extern int io_get_sh_swapper(nasid_t);
+#define BRIDGE_REG_GET32(reg) \
+ __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) )
+
+#define BRIDGE_REG_SET32(reg) \
+ *(volatile uint32_t *) (((uint64_t)reg)^4)
+#endif /* CONFIG_IA64_SGI_SN1 */
/* I/O page size */
@@ -36,6 +67,8 @@
#define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */
#define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */
+#define PIC_WR_REQ_BUFSIZE 256
+
#define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */
/* map to each device's */
/* config space */
@@ -78,7 +111,502 @@
* Generated from Bridge spec dated 04oct95
*/
-#ifdef LITTLE_ENDIAN
+#ifndef CONFIG_IA64_SGI_SN1
+
+/*
+ * pic_widget_cfg_s is a local definition of widget_cfg_t but with
+ * a union of 64bit & 32bit registers, since PIC has 64bit widget
+ * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that
+ * have valid bits (ie. not just reserved) in the upper 32bits are
+ * defined as a union so we can access them as 64bit for PIC and
+ * as 32bit for BRIDGE and XBRIDGE.
+ */
+typedef volatile struct pic_widget_cfg_s {
+ bridgereg_t _b_wid_id; /* 0x000004 */
+ bridgereg_t _pad_000000;
+
+ union {
+ picreg_t _p_wid_stat; /* 0x000008 */
+ struct {
+ bridgereg_t _b_wid_stat; /* 0x00000C */
+ bridgereg_t _b_pad_000008;
+ } _b;
+ } u_wid_stat;
+ #define __p_wid_stat_64 u_wid_stat._p_wid_stat
+ #define __b_wid_stat u_wid_stat._b._b_wid_stat
+
+ bridgereg_t _b_wid_err_upper; /* 0x000014 */
+ bridgereg_t _pad_000010;
+
+ union {
+ picreg_t _p_wid_err_lower; /* 0x000018 */
+ struct {
+ bridgereg_t _b_wid_err_lower; /* 0x00001C */
+ bridgereg_t _b_pad_000018;
+ } _b;
+ } u_wid_err_lower;
+ #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower
+ #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower
+
+ union {
+ picreg_t _p_wid_control; /* 0x000020 */
+ struct {
+ bridgereg_t _b_wid_control; /* 0x000024 */
+ bridgereg_t _b_pad_000020;
+ } _b;
+ } u_wid_control;
+ #define __p_wid_control_64 u_wid_control._p_wid_control
+ #define __b_wid_control u_wid_control._b._b_wid_control
+
+ bridgereg_t _b_wid_req_timeout; /* 0x00002C */
+ bridgereg_t _pad_000028;
+
+ bridgereg_t _b_wid_int_upper; /* 0x000034 */
+ bridgereg_t _pad_000030;
+
+ union {
+ picreg_t _p_wid_int_lower; /* 0x000038 */
+ struct {
+ bridgereg_t _b_wid_int_lower; /* 0x00003C */
+ bridgereg_t _b_pad_000038;
+ } _b;
+ } u_wid_int_lower;
+ #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower
+ #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower
+
+ bridgereg_t _b_wid_err_cmdword; /* 0x000044 */
+ bridgereg_t _pad_000040;
+
+ bridgereg_t _b_wid_llp; /* 0x00004C */
+ bridgereg_t _pad_000048;
+
+ bridgereg_t _b_wid_tflush; /* 0x000054 */
+ bridgereg_t _pad_000050;
+} pic_widget_cfg_t;
+
+/*
+ * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers
+ * were a 32bit quantity and double word aligned (and only accessable as a
+ * 32bit word. PIC registers are 64bits and accessable as words or double
+ * words. PIC registers that have valid bits (ie. not just reserved) in the
+ * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit
+ * bridgereg_t so we can access them both ways.
+ *
+ * It is generally preferred that hardware registers on the bridge are
+ * located from C code via this structure.
+ *
+ * Generated from Bridge spec dated 04oct95
+ */
+
+typedef volatile struct bridge_s {
+
+ /* 0x000000-0x00FFFF -- Local Registers */
+
+ /* 0x000000-0x000057 -- Standard Widget Configuration */
+ union {
+ widget_cfg_t xtalk_widget_def; /* 0x000000 */
+ pic_widget_cfg_t local_widget_def; /* 0x000000 */
+ } u_wid;
+
+ /* 32bit widget register access via the widget_cfg_t */
+ #define b_widget u_wid.xtalk_widget_def
+
+ /* 32bit widget register access via the pic_widget_cfg_t */
+ #define b_wid_id u_wid.local_widget_def._b_wid_id
+ #define b_wid_stat u_wid.local_widget_def.__b_wid_stat
+ #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper
+ #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower
+ #define b_wid_control u_wid.local_widget_def.__b_wid_control
+ #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout
+ #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper
+ #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower
+ #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword
+ #define b_wid_llp u_wid.local_widget_def._b_wid_llp
+ #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush
+
+ /* 64bit widget register access via the pic_widget_cfg_t */
+ #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64
+ #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64
+ #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64
+ #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64
+
+ /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
+ bridgereg_t b_wid_aux_err; /* 0x00005C */
+ bridgereg_t _pad_000058;
+
+ bridgereg_t b_wid_resp_upper; /* 0x000064 */
+ bridgereg_t _pad_000060;
+
+ union {
+ picreg_t _p_wid_resp_lower; /* 0x000068 */
+ struct {
+ bridgereg_t _b_wid_resp_lower; /* 0x00006C */
+ bridgereg_t _b_pad_000068;
+ } _b;
+ } u_wid_resp_lower;
+ #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower
+ #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower
+
+ bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
+ bridgereg_t _pad_000070;
+
+ union {
+ picreg_t _p_addr_lkerr; /* 0x000078 */
+ struct {
+ bridgereg_t _b_pad_00007C;
+ bridgereg_t _b_pad_000078;
+ } _b;
+ } u_addr_lkerr;
+ #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr
+
+ /* 0x000080-0x00008F -- PMU */
+ bridgereg_t b_dir_map; /* 0x000084 */
+ bridgereg_t _pad_000080;
+
+ bridgereg_t _pad_00008C;
+ bridgereg_t _pad_000088;
+
+ /* 0x000090-0x00009F -- SSRAM */
+ bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */
+ bridgereg_t _pad_000090;
+ #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */
+ #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */
+
+ bridgereg_t _pad_00009C;
+ bridgereg_t _pad_000098;
+
+ /* 0x0000A0-0x0000AF -- Arbitration */
+ bridgereg_t b_arb; /* 0x0000A4 */
+ bridgereg_t _pad_0000A0;
+
+ bridgereg_t _pad_0000AC;
+ bridgereg_t _pad_0000A8;
+
+ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+ union {
+ picreg_t _p_ate_parity_err; /* 0x0000B0 */
+ struct {
+ bridgereg_t _b_nic; /* 0x0000B4 */
+ bridgereg_t _b_pad_0000B0;
+ } _b;
+ } u_ate_parity_err_or_nic;
+ #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err
+ #define b_nic u_ate_parity_err_or_nic._b._b_nic
+
+ bridgereg_t _pad_0000BC;
+ bridgereg_t _pad_0000B8;
+
+ /* 0x0000C0-0x0000FF -- PCI/GIO */
+ bridgereg_t b_bus_timeout; /* 0x0000C4 */
+ bridgereg_t _pad_0000C0;
+ #define b_pci_bus_timeout b_bus_timeout
+
+ bridgereg_t b_pci_cfg; /* 0x0000CC */
+ bridgereg_t _pad_0000C8;
+
+ bridgereg_t b_pci_err_upper; /* 0x0000D4 */
+ bridgereg_t _pad_0000D0;
+ #define b_gio_err_upper b_pci_err_upper
+
+ union {
+ picreg_t _p_pci_err_lower; /* 0x0000D8 */
+ struct {
+ bridgereg_t _b_pci_err_lower; /* 0x0000DC */
+ bridgereg_t _b_pad_0000D8;
+ } _b;
+ } u_pci_err_lower;
+ #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower
+ #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower
+ #define b_gio_err_lower b_pci_err_lower
+
+ bridgereg_t _pad_0000E0[8];
+
+ /* 0x000100-0x0001FF -- Interrupt */
+ union {
+ picreg_t _p_int_status; /* 0x000100 */
+ struct {
+ bridgereg_t _b_int_status; /* 0x000104 */
+ bridgereg_t _b_pad_000100;
+ } _b;
+ } u_int_status;
+ #define p_int_status_64 u_int_status._p_int_status
+ #define b_int_status u_int_status._b._b_int_status
+
+ union {
+ picreg_t _p_int_enable; /* 0x000108 */
+ struct {
+ bridgereg_t _b_int_enable; /* 0x00010C */
+ bridgereg_t _b_pad_000108;
+ } _b;
+ } u_int_enable;
+ #define p_int_enable_64 u_int_enable._p_int_enable
+ #define b_int_enable u_int_enable._b._b_int_enable
+
+ union {
+ picreg_t _p_int_rst_stat; /* 0x000110 */
+ struct {
+ bridgereg_t _b_int_rst_stat; /* 0x000114 */
+ bridgereg_t _b_pad_000110;
+ } _b;
+ } u_int_rst_stat;
+ #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat
+ #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat
+
+ bridgereg_t b_int_mode; /* 0x00011C */
+ bridgereg_t _pad_000118;
+
+ bridgereg_t b_int_device; /* 0x000124 */
+ bridgereg_t _pad_000120;
+
+ bridgereg_t b_int_host_err; /* 0x00012C */
+ bridgereg_t _pad_000128;
+
+ union {
+ picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */
+ struct {
+ bridgereg_t addr; /* 0x0001{34,,,6C} */
+ bridgereg_t _b_pad;
+ } _b[8];
+ } u_int_addr;
+ #define p_int_addr_64 u_int_addr._p_int_addr
+ #define b_int_addr u_int_addr._b
+
+ union {
+ picreg_t _p_err_int_view; /* 0x000170 */
+ struct {
+ bridgereg_t _b_err_int_view; /* 0x000174 */
+ bridgereg_t _b_pad_000170;
+ } _b;
+ } u_err_int_view;
+ #define p_err_int_view_64 u_err_int_view._p_err_int_view
+ #define b_err_int_view u_err_int_view._b._b_err_int_view
+
+ union {
+ picreg_t _p_mult_int; /* 0x000178 */
+ struct {
+ bridgereg_t _b_mult_int; /* 0x00017C */
+ bridgereg_t _b_pad_000178;
+ } _b;
+ } u_mult_int;
+ #define p_mult_int_64 u_mult_int._p_mult_int
+ #define b_mult_int u_mult_int._b._b_mult_int
+
+ struct {
+ bridgereg_t intr; /* 0x0001{84,,,BC} */
+ bridgereg_t __pad;
+ } b_force_always[8];
+
+ struct {
+ bridgereg_t intr; /* 0x0001{C4,,,FC} */
+ bridgereg_t __pad;
+ } b_force_pin[8];
+
+ /* 0x000200-0x0003FF -- Device */
+ struct {
+ bridgereg_t reg; /* 0x0002{04,,,3C} */
+ bridgereg_t __pad;
+ } b_device[8];
+
+ struct {
+ bridgereg_t reg; /* 0x0002{44,,,7C} */
+ bridgereg_t __pad;
+ } b_wr_req_buf[8];
+
+ struct {
+ bridgereg_t reg; /* 0x0002{84,,,8C} */
+ bridgereg_t __pad;
+ } b_rrb_map[2];
+ #define b_even_resp b_rrb_map[0].reg /* 0x000284 */
+ #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
+
+ bridgereg_t b_resp_status; /* 0x000294 */
+ bridgereg_t _pad_000290;
+
+ bridgereg_t b_resp_clear; /* 0x00029C */
+ bridgereg_t _pad_000298;
+
+ bridgereg_t _pad_0002A0[24];
+
+ /* Xbridge/PIC only */
+ union {
+ struct {
+ picreg_t lower; /* 0x0003{08,,,F8} */
+ picreg_t upper; /* 0x0003{00,,,F0} */
+ } _p[16];
+ struct {
+ bridgereg_t upper; /* 0x0003{04,,,F4} */
+ bridgereg_t _b_pad1;
+ bridgereg_t lower; /* 0x0003{0C,,,FC} */
+ bridgereg_t _b_pad2;
+ } _b[16];
+ } u_buf_addr_match;
+ #define p_buf_addr_match_64 u_buf_addr_match._p
+ #define b_buf_addr_match u_buf_addr_match._b
+
+ /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+ struct {
+ bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */
+ bridgereg_t __pad1;
+ bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */
+ bridgereg_t __pad2;
+ bridgereg_t inflight; /* 0x000{414,,,5D4} */
+ bridgereg_t __pad3;
+ bridgereg_t prefetch; /* 0x000{41C,,,5DC} */
+ bridgereg_t __pad4;
+ bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */
+ bridgereg_t __pad5;
+ bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */
+ bridgereg_t __pad6;
+ bridgereg_t max_latency; /* 0x000{434,,,5F4} */
+ bridgereg_t __pad7;
+ bridgereg_t clear_all; /* 0x000{43C,,,5FC} */
+ bridgereg_t __pad8;
+ } b_buf_count[8];
+
+ /*
+ * "PCI/X registers that are specific to PIC". See pic.h.
+ */
+
+ /* 0x000600-0x0009FF -- PCI/X registers */
+ picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */
+ picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */
+ picreg_t p_pcix_bus_err_data_64; /* 0x000610 */
+ picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */
+ picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */
+ picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */
+ picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */
+ picreg_t p_pcix_timeout_64; /* 0x000638 */
+
+ picreg_t _pad_000600[120];
+
+ /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+ struct {
+ picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */
+ picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */
+ } p_pcix_read_buf_64[16];
+
+ struct {
+ picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */
+ picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */
+ picreg_t __pad1; /* 0x000{B18,,,BF8} */
+ picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */
+ } p_pcix_write_buf_64[8];
+
+ /*
+ * end "PCI/X registers that are specific to PIC"
+ */
+
+ char _pad_000c00[0x010000 - 0x000c00];
+
+ /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */
+ /*
+ * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128.
+ * Make enough room for the Xbridge/PIC ATE's and depend on runtime
+ * checks to limit access to bridge ATE's.
+ *
+ * In [X]bridge the internal ATE Ram is writen as double words only,
+ * but due to internal design issues it is read back as single words.
+ * i.e:
+ * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd
+ */
+ union {
+ bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */
+ struct {
+ bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */
+ bridgereg_t _p_pad;
+ } hi;
+ } b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
+ #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
+
+ /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */
+ struct {
+ bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */
+ bridgereg_t _p_pad;
+ } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
+
+ char _pad_014000[0x18000 - 0x014000];
+
+ /* 0x18000-0x197F8 -- PIC Write Request Ram */
+ /* 0x18000 - 0x187F8 */
+ picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE];
+ /* 0x18800 - 0x18FF8 */
+ picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE];
+ /* 0x19000 - 0x197F8 */
+ picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE];
+
+ char _pad_019800[0x20000 - 0x019800];
+
+ /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
+ union { /* make all access sizes available. */
+ uchar_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
+ uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
+ uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
+ uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
+ union {
+ uchar_t c[0x100 / 1];
+ uint16_t s[0x100 / 2];
+ uint32_t l[0x100 / 4];
+ uint64_t d[0x100 / 8];
+ } f[8];
+ } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
+
+ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+ union { /* make all access sizes available. */
+ uchar_t c[0x1000 / 1];
+ uint16_t s[0x1000 / 2];
+ uint32_t l[0x1000 / 4];
+ uint64_t d[0x1000 / 8];
+ union {
+ uchar_t c[0x100 / 1];
+ uint16_t s[0x100 / 2];
+ uint32_t l[0x100 / 4];
+ uint64_t d[0x100 / 8];
+ } f[8];
+ } b_type1_cfg; /* 0x028000-0x029000 */
+
+ char _pad_029000[0x007000]; /* 0x029000-0x030000 */
+
+ /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+ union {
+ uchar_t c[8 / 1];
+ uint16_t s[8 / 2];
+ uint32_t l[8 / 4];
+ uint64_t d[8 / 8];
+ } b_pci_iack; /* 0x030000-0x030007 */
+
+ uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
+
+ /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */
+ bridge_ate_t b_ext_ate_ram[0x10000];
+
+ /* 0x100000-0x1FFFFF -- Reserved */
+ char _pad_100000[0x200000-0x100000];
+
+ /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */
+ union { /* make all access sizes available. */
+ uchar_t c[0x100000 / 1];
+ uint16_t s[0x100000 / 2];
+ uint32_t l[0x100000 / 4];
+ uint64_t d[0x100000 / 8];
+ } b_devio_raw[10];
+
+ /* b_devio macro is a bit strange; it reflects the
+ * fact that the Bridge ASIC provides 2M for the
+ * first two DevIO windows and 1M for the other six.
+ */
+ #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+ /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */
+ union { /* make all access sizes available. */
+ uchar_t c[0x400000 / 1]; /* read-only */
+ uint16_t s[0x400000 / 2]; /* read-write */
+ uint32_t l[0x400000 / 4]; /* read-only */
+ uint64_t d[0x400000 / 8]; /* read-only */
+ } b_external_flash;
+} bridge_t;
+
+#else /* CONFIG_IA64_SGI_SN1 */
+
typedef volatile struct bridge_s {
@@ -311,6 +839,12 @@
uint16_t s[0x1000 / 2];
uint32_t l[0x1000 / 4];
uint64_t d[0x1000 / 8];
+ union {
+ uchar_t c[0x100 / 1];
+ uint16_t s[0x100 / 2];
+ uint32_t l[0x100 / 4];
+ uint64_t d[0x100 / 8];
+ } f[8];
} b_type1_cfg; /* 0x028000-0x029000 */
char _pad_029000[0x007000]; /* 0x029000-0x030000 */
@@ -354,286 +888,7 @@
} b_external_flash; /* 0xC00000 */
} bridge_t;
-#else
-
-/*
- * Field formats for Error Command Word and Auxillary Error Command Word
- * of bridge.
- */
-typedef struct bridge_err_cmdword_s {
- union {
- uint32_t cmd_word;
- struct {
- uint32_t didn:4, /* Destination ID */
- sidn:4, /* SOurce ID */
- pactyp:4, /* Packet type */
- tnum:5, /* Trans Number */
- coh:1, /* Coh Transacti */
- ds:2, /* Data size */
- gbr:1, /* GBR enable */
- vbpm:1, /* VBPM message */
- error:1, /* Error occurred */
- barr:1, /* Barrier op */
- rsvd:8;
- } berr_st;
- } berr_un;
-} bridge_err_cmdword_t;
-
-typedef volatile struct bridge_s {
-
- /* Local Registers 0x000000-0x00FFFF */
-
- /* standard widget configuration 0x000000-0x000057 */
- widget_cfg_t b_widget; /* 0x000000 */
-
- /* helper fieldnames for accessing bridge widget */
-
-#define b_wid_id b_widget.w_id
-#define b_wid_stat b_widget.w_status
-#define b_wid_err_upper b_widget.w_err_upper_addr
-#define b_wid_err_lower b_widget.w_err_lower_addr
-#define b_wid_control b_widget.w_control
-#define b_wid_req_timeout b_widget.w_req_timeout
-#define b_wid_int_upper b_widget.w_intdest_upper_addr
-#define b_wid_int_lower b_widget.w_intdest_lower_addr
-#define b_wid_err_cmdword b_widget.w_err_cmd_word
-#define b_wid_llp b_widget.w_llp_cfg
-#define b_wid_tflush b_widget.w_tflush
-
- /* bridge-specific widget configuration 0x000058-0x00007F */
- bridgereg_t _pad_000058;
- bridgereg_t b_wid_aux_err; /* 0x00005C */
- bridgereg_t _pad_000060;
- bridgereg_t b_wid_resp_upper; /* 0x000064 */
- bridgereg_t _pad_000068;
- bridgereg_t b_wid_resp_lower; /* 0x00006C */
- bridgereg_t _pad_000070;
- bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
- bridgereg_t _pad_000078[2];
-
- /* PMU & Map 0x000080-0x00008F */
- bridgereg_t _pad_000080;
- bridgereg_t b_dir_map; /* 0x000084 */
- bridgereg_t _pad_000088[2];
-
- /* SSRAM 0x000090-0x00009F */
- bridgereg_t _pad_000090;
- bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */
-#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */
-#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */
- bridgereg_t _pad_000098[2];
-
- /* Arbitration 0x0000A0-0x0000AF */
- bridgereg_t _pad_0000A0;
- bridgereg_t b_arb; /* 0x0000A4 */
- bridgereg_t _pad_0000A8[2];
-
- /* Number In A Can 0x0000B0-0x0000BF */
- bridgereg_t _pad_0000B0;
- bridgereg_t b_nic; /* 0x0000B4 */
- bridgereg_t _pad_0000B8[2];
-
- /* PCI/GIO 0x0000C0-0x0000FF */
- bridgereg_t _pad_0000C0;
- bridgereg_t b_bus_timeout; /* 0x0000C4 */
-#define b_pci_bus_timeout b_bus_timeout
-
- bridgereg_t _pad_0000C8;
- bridgereg_t b_pci_cfg; /* 0x0000CC */
- bridgereg_t _pad_0000D0;
- bridgereg_t b_pci_err_upper; /* 0x0000D4 */
- bridgereg_t _pad_0000D8;
- bridgereg_t b_pci_err_lower; /* 0x0000DC */
- bridgereg_t _pad_0000E0[8];
-#define b_gio_err_lower b_pci_err_lower
-#define b_gio_err_upper b_pci_err_upper
-
- /* Interrupt 0x000100-0x0001FF */
- bridgereg_t _pad_000100;
- bridgereg_t b_int_status; /* 0x000104 */
- bridgereg_t _pad_000108;
- bridgereg_t b_int_enable; /* 0x00010C */
- bridgereg_t _pad_000110;
- bridgereg_t b_int_rst_stat; /* 0x000114 */
- bridgereg_t _pad_000118;
- bridgereg_t b_int_mode; /* 0x00011C */
- bridgereg_t _pad_000120;
- bridgereg_t b_int_device; /* 0x000124 */
- bridgereg_t _pad_000128;
- bridgereg_t b_int_host_err; /* 0x00012C */
-
- struct {
- bridgereg_t __pad; /* 0x0001{30,,,68} */
- bridgereg_t addr; /* 0x0001{34,,,6C} */
- } b_int_addr[8]; /* 0x000130 */
-
- bridgereg_t _pad_000170;
- bridgereg_t b_err_int_view; /* 0x000174 */
- bridgereg_t _pad_000178;
- bridgereg_t b_mult_int; /* 0x00017c */
-
- struct {
- bridgereg_t __pad; /* 0x0001{80,,,B8} */
- bridgereg_t intr; /* 0x0001{84,,,BC} */
- } b_force_always[8]; /* 0x000180 */
-
- struct {
- bridgereg_t __pad; /* 0x0001{C0,,,F8} */
- bridgereg_t intr; /* 0x0001{C4,,,FC} */
- } b_force_pin[8]; /* 0x0001C0 */
-
- /* Device 0x000200-0x0003FF */
- struct {
- bridgereg_t __pad; /* 0x0002{00,,,38} */
- bridgereg_t reg; /* 0x0002{04,,,3C} */
- } b_device[8]; /* 0x000200 */
-
- struct {
- bridgereg_t __pad; /* 0x0002{40,,,78} */
- bridgereg_t reg; /* 0x0002{44,,,7C} */
- } b_wr_req_buf[8]; /* 0x000240 */
-
- struct {
- bridgereg_t __pad; /* 0x0002{80,,,88} */
- bridgereg_t reg; /* 0x0002{84,,,8C} */
- } b_rrb_map[2]; /* 0x000280 */
-#define b_even_resp b_rrb_map[0].reg /* 0x000284 */
-#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
-
- bridgereg_t _pad_000290;
- bridgereg_t b_resp_status; /* 0x000294 */
- bridgereg_t _pad_000298;
- bridgereg_t b_resp_clear; /* 0x00029C */
-
- bridgereg_t _pad_0002A0[24];
-
- /* Xbridge only */
- struct {
- bridgereg_t __pad1; /* 0x0003{00,,,F0} */
- bridgereg_t upper; /* 0x0003{04,,,F4} */
- bridgereg_t __pad2; /* 0x0003{08,,,F8} */
- bridgereg_t lower; /* 0x0003{0C,,,FC} */
- } b_buf_addr_match[16];
-
- /* Performance Monitor Registers (even only) */
- struct {
- bridgereg_t __pad1; /* 0x000400,,,5C0 */
- bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */
- bridgereg_t __pad2; /* 0x000408,,,5C8 */
- bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */
- bridgereg_t __pad3; /* 0x000410,,,5D0 */
- bridgereg_t inflight; /* 0x000414,,,5D4 */
- bridgereg_t __pad4; /* 0x000418,,,5D8 */
- bridgereg_t prefetch; /* 0x00041C,,,5DC */
- bridgereg_t __pad5; /* 0x000420,,,5E0 */
- bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */
- bridgereg_t __pad6; /* 0x000428,,,5E8 */
- bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */
- bridgereg_t __pad7; /* 0x000430,,,5F0 */
- bridgereg_t max_latency; /* 0x000434,,,5F4 */
- bridgereg_t __pad8; /* 0x000438,,,5F8 */
- bridgereg_t clear_all; /* 0x00043C,,,5FC */
- } b_buf_count[8];
-
- char _pad_000600[0x010000 - 0x000600];
-
- /*
- * The Xbridge has 1024 internal ATE's and the Bridge has 128.
- * Make enough room for the Xbridge ATE's and depend on runtime
- * checks to limit access to bridge ATE's.
- */
-
- /* Internal Address Translation Entry RAM 0x010000-0x011fff */
- union {
- bridge_ate_t wr; /* write-only */
- struct {
- bridgereg_t _p_pad;
- bridgereg_t rd; /* read-only */
- } hi;
- } b_int_ate_ram[XBRIDGE_INTERNAL_ATES];
-
-#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd
-
- /* the xbridge read path for internal ates starts at 0x12000.
- * I don't believe we ever try to read the ates.
- */
- /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */
- struct {
- bridgereg_t _p_pad;
- bridgereg_t rd; /* read-only */
- } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];
-
- char _pad_014000[0x20000 - 0x014000];
-
- /* PCI Device Configuration Spaces 0x020000-0x027FFF */
- union { /* make all access sizes available. */
- uchar_t c[0x1000 / 1];
- uint16_t s[0x1000 / 2];
- uint32_t l[0x1000 / 4];
- uint64_t d[0x1000 / 8];
- union {
- uchar_t c[0x100 / 1];
- uint16_t s[0x100 / 2];
- uint32_t l[0x100 / 4];
- uint64_t d[0x100 / 8];
- } f[8];
- } b_type0_cfg_dev[8]; /* 0x020000 */
-
-
- /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
- union { /* make all access sizes available. */
- uchar_t c[0x1000 / 1];
- uint16_t s[0x1000 / 2];
- uint32_t l[0x1000 / 4];
- uint64_t d[0x1000 / 8];
- } b_type1_cfg; /* 0x028000-0x029000 */
-
- char _pad_029000[0x007000]; /* 0x029000-0x030000 */
-
- /* PCI Interrupt Acknowledge Cycle 0x030000 */
- union {
- uchar_t c[8 / 1];
- uint16_t s[8 / 2];
- uint32_t l[8 / 4];
- uint64_t d[8 / 8];
- } b_pci_iack; /* 0x030000 */
-
- uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
-
- /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
- bridge_ate_t b_ext_ate_ram[0x10000];
-
- /* Reserved 0x100000-0x1FFFFF */
- char _pad_100000[0x200000-0x100000];
-
- /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
- union { /* make all access sizes available. */
- uchar_t c[0x100000 / 1];
- uint16_t s[0x100000 / 2];
- uint32_t l[0x100000 / 4];
- uint64_t d[0x100000 / 8];
- } b_devio_raw[10]; /* 0x200000 */
-
- /* b_devio macro is a bit strange; it reflects the
- * fact that the Bridge ASIC provides 2M for the
- * first two DevIO windows and 1M for the other six.
- */
-#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
-
- /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
- union { /* make all access sizes available. */
- uchar_t c[0x400000 / 1]; /* read-only */
- uint16_t s[0x400000 / 2]; /* read-write */
- uint32_t l[0x400000 / 4]; /* read-only */
- uint64_t d[0x400000 / 8]; /* read-only */
- } b_external_flash; /* 0xC00000 */
-} bridge_t;
-
-#endif
-
-
-
-
+#endif /* CONFIG_IA64_SGI_SN1 */
#define berr_field berr_un.berr_st
@@ -873,7 +1128,12 @@
/* end of Performance Monitor Registers */
-/* Byte offset macros for Bridge I/O space */
+/* Byte offset macros for Bridge I/O space.
+ *
+ * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx
+ * macros (below) as they will handle [X]Bridge and PIC. For example,
+ * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0
+ */
#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
@@ -905,7 +1165,55 @@
#ifndef __ASSEMBLY__
#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
-#endif /* __ASSEMBLY__ */
+
+/*
+ * The device space macros for PIC are more complicated because the PIC has
+ * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are
+ * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are
+ * offset by 0x800000. Here are two sets of macros. They are
+ * "PCIBRIDGE_xxx" that return the address based on the supplied bus number
+ * and also equivalent "PCIBR_xxx" macros that may be used with a
+ * pcibr_soft_s structure. Both should work with all bridges.
+ */
+#define PIC_BUS1_OFFSET 0x800000
+
+#define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \
+ ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \
+ BRIDGE_TYPE0_CFG_DEV0)
+#define PCIBRIDGE_TYPE1_CFG(busnum) \
+ ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG)
+#define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \
+ (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
+#define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \
+ (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\
+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
+#define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \
+ (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0)
+#define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \
+ (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1)
+#define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \
+ (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2)
+#define PCIBRIDGE_DEVIO(busnum, x) \
+ ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \
+ PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB)
+
+#define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum)
+#define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum)
+#define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum)
+#define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s)
+
+#define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum)
+#define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0)
+#define PCIBR_TYPE0_CFG_DEV(ps, s) \
+ ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \
+ PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s))
+#define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \
+ ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \
+ PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f))
+
+#endif /* LANGUAGE_C */
#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
@@ -929,6 +1237,17 @@
#define XBRIDGE_REV_A 0x1
#define XBRIDGE_REV_B 0x2
+/* macros to determine bridge type. 'wid' == widget identification */
+#define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \
+ XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM)
+#define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \
+ XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM)
+#define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \
+ XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
+#define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \
+ XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
+#define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid))
+
/* Part + Rev numbers allows distinction and acscending sequence */
#define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A)
#define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B)
@@ -938,7 +1257,8 @@
#define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B)
/* Bridge widget status register bits definition */
-
+#define PIC_STAT_PCIX_SPEED (0x3ull << 34)
+#define PIC_STAT_PCIX_ACTIVE (0x1ull << 33)
#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
@@ -946,7 +1266,18 @@
#define BRIDGE_STAT_PENDING (0x1F << 0)
/* Bridge widget control register bits definition */
-#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
+#define PIC_CTRL_NO_SNOOP (0x1ull << 62)
+#define PIC_CTRL_RELAX_ORDER (0x1ull << 61)
+#define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48)
+#define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff))
+#define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43)
+#define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f))
+#define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40)
+#define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7))
+#define PIC_CTRL_PAR_EN_REQ (0x1ull << 29)
+#define PIC_CTRL_PAR_EN_RESP (0x1ull << 30)
+#define PIC_CTRL_PAR_EN_ATE (0x1ull << 31)
+#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */
#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
@@ -970,6 +1301,8 @@
#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
#define BRIDGE_CTRL_SYS_END (0x1 << 9)
+#define BRIDGE_CTRL_PCI_SPEED (0x3 << 4)
+
#define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4)
#define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3))
#define BRIDGE_CTRL_BUS_SPEED_33 0x00
@@ -1023,6 +1356,20 @@
#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
/* Bridge interrupt status register bits definition */
+#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45)
+#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44)
+#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43)
+#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42)
+#define PIC_ISR_INT_RAM_PERR (0x1ull << 41)
+#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40)
+#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39)
+#define PIC_ISR_PCIX_TABORT (0x1ull << 38)
+#define PIC_ISR_PCIX_PERR (0x1ull << 37)
+#define PIC_ISR_PCIX_SERR (0x1ull << 36)
+#define PIC_ISR_PCIX_MRETRY (0x1ull << 35)
+#define PIC_ISR_PCIX_MTOUT (0x1ull << 34)
+#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33)
+#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32)
#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */
#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */
#define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */
@@ -1058,12 +1405,18 @@
BRIDGE_ISR_LLP_TCTY)
#define BRIDGE_ISR_PCIBUS_PIOERR \
- (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+ (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \
+ PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)
#define BRIDGE_ISR_PCIBUS_ERROR \
(BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \
BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \
- BRIDGE_ISR_PCI_PARITY)
+ BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \
+ PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \
+ PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \
+ PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \
+ PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \
+ PIC_ISR_PCIX_SPLIT_MSG_PE)
#define BRIDGE_ISR_XTALK_ERROR \
(BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
@@ -1075,20 +1428,39 @@
#define BRIDGE_ISR_ERRORS \
(BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \
BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
- BRIDGE_ISR_PMU_ESIZE_FAULT)
+ BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_PCIX_ARB_ERR| \
+ PIC_ISR_INT_RAM_PERR)
/*
* List of Errors which are fatal and kill the sytem
*/
#define BRIDGE_ISR_ERROR_FATAL \
((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
- BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+ BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \
+ PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \
+ PIC_ISR_PCIX_DA_PARITY| \
+ PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE )
#define BRIDGE_ISR_ERROR_DUMP \
(BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \
- BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
+ PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR)
/* Bridge interrupt enable register bits definition */
+#define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE
+#define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG
+#define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO
+#define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP
+#define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR
+#define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR
+#define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT
+#define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT
+#define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR
+#define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR
+#define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY
+#define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT
+#define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY
+#define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY
#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
@@ -1116,7 +1488,46 @@
#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
-/* Bridge interrupt reset register bits definition */
+/*
+ * Bridge interrupt reset register bits definition. Note, PIC can
+ * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do
+ * groups of them.
+ */
+#define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE
+#define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG
+#define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO
+#define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP
+#define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR
+#define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR
+#define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT
+#define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT
+#define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR
+#define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR
+#define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY
+#define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT
+#define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY
+#define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY
+#define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT
+#define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
+#define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
+#define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
+#define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
+#define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
+#define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
+#define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
+#define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
+#define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
+#define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
+#define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
+#define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
+#define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
+#define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
+#define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
+#define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR
+#define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR
+#define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
+#define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
+#define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
@@ -1153,6 +1564,21 @@
#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \
BRIDGE_ISR_GIO_MST_TIMEOUT)
+#define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR
+
+#define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \
+ PIC_IRR_PCIX_DA_PARITY | \
+ PIC_IRR_PCIX_MTOUT | \
+ PIC_IRR_PCIX_MRETRY | \
+ PIC_IRR_PCIX_SERR | \
+ PIC_IRR_PCIX_PERR | \
+ PIC_IRR_PCIX_TABORT | \
+ PIC_ISR_PCIX_REQ_TOUT | \
+ PIC_ISR_PCIX_UNEX_COMP | \
+ PIC_ISR_PCIX_SPLIT_TO | \
+ PIC_ISR_PCIX_SPLIT_EMSG | \
+ PIC_ISR_PCIX_SPLIT_MSG_PE)
+
/* Bridge INT_DEV register bits definition */
#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
@@ -1162,6 +1588,10 @@
#define BRIDGE_INT_ADDR_HOST 0x0003FF00
#define BRIDGE_INT_ADDR_FLD 0x000000FF
+/* PIC interrupt(x) register bits definition */
+#define PIC_INT_ADDR_FLD 0x00FF000000000000
+#define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF
+
#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
@@ -1239,8 +1669,13 @@
/* RRB assignment register */
#define BRIDGE_RRB_EN 0x8 /* after shifting down */
#define BRIDGE_RRB_DEV 0x7 /* after shifting down */
-#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
-#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
+#define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */
+#define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */
+
+#define PIC_RRB_EN 0x8 /* after shifting down */
+#define PIC_RRB_DEV 0x7 /* after shifting down */
+#define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */
+#define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */
/* RRB status register */
#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
@@ -1249,6 +1684,15 @@
/* RRB clear register */
#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
+/* Defines for the virtual channels so we dont hardcode 0-3 within code */
+#define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */
+#define VCHAN1 1 /* virtual channel 1 */
+#define VCHAN2 2 /* virtual channel 2 - PIC only */
+#define VCHAN3 3 /* virtual channel 3 - PIC only */
+
+/* PIC: PCI-X Read Buffer Attribute Register (RBAR) */
+#define NUM_RBAR 16 /* number of RBAR registers */
+
/* xbox system controller declarations */
#define XBOX_BRIDGE_WID 8
#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */
@@ -1401,8 +1845,10 @@
#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
-#define is_xbridge(bridge) \
- (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM)
+#define is_xbridge(bridge) IS_XBRIDGE(bridge->b_wid_id)
+#define is_pic(bridge) IS_PIC_BRIDGE(bridge->b_wid_id)
+
+/* extern declarations */
#ifndef __ASSEMBLY__
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)